The present invention generally relates to an improved external memory accessing system and more particularly to an external memory accessing system for a reduced instruction set (RISC) processor which employs register-indirect addressing and external memory.
Microprocessors are well known in the art. One type of microprocessor is a reduced instruction set (RISC) processor having a pipelined architecture. Such processors process serial instructions through a series of stages including, for example, a fetch stage, a decode stage, an execute stage, and a write-back stage. Such processors operate at very high speeds and due to their pipelined architecture, are capable of efficiently executing instructions with a minimum of hardware.
In such processors, each instruction is processed through the aforementioned stages. Hence, a first instruction may be in the decode stage while a second or next instruction is being fetched. In the next cycle, both instructions move down the pipeline by one stage wherein the first instruction is now being executed while the second instruction is being decoded.
When a processor of this type is called upon by an instruction to perform an execution upon data, it does so by acting upon the operands contained in a register file. Hence, in order to execute such instructions, it is first necessary for the processor to load the data or operands into register file. As a result, load instructions are common in such processors for this purpose.
In order to load data into a register file from an external memory, the external memory must first be accessed. In order to access external memory, prior art processors must first compute the address of the external memory and then translate the address into a physical address of the external memory. This process takes time and can adversely affect the efficiency of the processor. Other processors compute the external memory address before the load instruction and store the address for later use. However, such processors still must translate the address after the load instruction. While this type of processor exhibits improvement over the first-mentioned processor, improvement on this process is still desireable.
A high-performance processor requires low latency access to an external memory in order to achieve its potential performance. Preferably, the memory should supply an item of data within one cycle after the processor requests it. The term "zero-wait-state" is commonly applied to a memory system with this capability. This refers to the fact that the processor does not have to wait for a memory access to complete, because the access is always completed quickly.
Unfortunately, the technical requirements on a zero-wait-state memory make it very difficult and expensive to implement. This is particularly true at the very high operating frequencies that characterize RISC processors. The combined requirements for zero-wait-state memory and very high operating frequencies present a severe impediment to the performance of these types of processors.
The present invention overcomes the aforementioned problems with respect to accessing an external memory. The present invention, while using a one-wait-state memory system is capable of achieving the performance of a zero-wait-state memory.